Dynamic random-access memory (DRAM) devices utilize capacitors to store bits of data in an integrated circuit. In a conventional DRAM memory cell, a metal-oxide-semiconductor field-effect transistor (MOSFET) functions as a control switch and a capacitor stores charges corresponding to data that is to be stored. A capacitor, for example, can be charged or discharged, representing two values of a bit, conventionally referred to as 0 and 1. Capacitance increases with the surface area of the capacitor and high capacitance prevents loss of stored data. The way to increase the charge-storing capacity of a capacitor is to increase the dielectric coefficient of the dielectric material and reduce the thickness of the dielectric material, plus increasing the surface area of the capacitor.
Planar type capacitors undesirably occupy a large area of a semiconductor substrate and are not suited for high or large-scale integration. Highly-integrated DRAM devices may employ stacked capacitors, which occupy less area of the semiconductor substrate, while also allowing for increases in surface area and corresponding capacitance of the capacitor.
Memory devices can be stacked in a three-dimensional (3D) configuration in a stackable cross-gridded data access array, referred to as a crossbar array. Crossbar configurations have been applied to devices implementing neural networks.
There is a need for memory devices and structures utilizing stacked capacitors in connection with a crossbar neural network.